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Low Power Bit - Parallel Cellular Multiplier Implemetation in Secure Dual - Rail Adiabatic Logic | ||
| Author Name | : Cancio Monteiro, Ph.D. |
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| Category | : Internasional Publication | |
| Published in | : Japan 2013 | |
| Publication File | : No File Uploaded | |
| Link | : http://www.ijmo.org/index.php?m=content&c=index&a=show&catid=38&id=312papers/292-CS0011.pdf | |
Abstract - The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(24). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155mm2, and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×173 mm2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.
Index Terms - B it -parallel multiplier, diabatic, low-power, side channel attack, cryptography.
