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Process Variation Verification Of Low-Power Secure Cssal Aes S-Box Circuit | ||
| Author Name | : Cancio Monteiro, Ph.D. |
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| Category | : Internasional Publication | |
| Published in | : Japan 2011 | |
| Publication File | : No File Uploaded | |
| Link | : https://monteirocancio.wordpress.com/publications/ | |
Abstract
In this work, we implement our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using a multi-stage positive polarity Reed-Muller (PPRM) representation with a composite field technique. We evaluate the effectiveness of the CSSAL S-box circuit against side-channel attacks towards the variations of the CMOS process technology. The results of this paper are obtained from the SPICE simulation with 0.18-μm and 90-nm standard CMOS technology at an operating frequency band of 125 KHz-70 MHz.
