FECT

Abstract: This paper presents a proposed Two Memristor—Six Transistor—Static Random Access Memory (2M-6T-SRAM) cells and compares its read/write operation with the conventional 6T-SRAM cell circuit. The authors further investigate the energy consumption of conventional CMOS 6T-SRAM versus proposed 2M-6T-SRAM cell-based Memristor.  The power dissipation in conventional CMOS 6T-SARAM can be minimized through 2M-6T-SRAM cell design technique, because the two Memristors are connected to a pull-up network to control the leakage current. The static noise margins of the SRAM cells are also presented and compared among the circuit topologies. The simulation result shows that the proposed 2M-6T-SRAM cell based Memristor reduces energy about 65 % from the one of the conventional 6T-SRAM at 10 MHz frequency speed using 0.18 um CMOS process technology. In addition, the proposed circuit effective operation speed is from 50 KHz—1 GHz, which is applicable to any device within these frequency ranges.

     Keywords: memristor, SNM, 6T-SRAM, memristor-based SRAM, low-power.