FECT

Abstract: According to the Moore’s Law, the number of transistors in a unit chip area double every two years. However, the existing technology of integrated circuit formation is posing limitations to this law. Based on the International Technology Roadmap for Semiconductors (ITRS), beyond 32nm technology node, planer devices will not be able to fulfill the strict leakage requirement anymore due to overpowering short channel effects and need of multi-gate transistor is inevitable. FinFET is evolving to be a promising technology in this regard. This paper aims to investigate leakage power consumption on adiabatic circuit based on CMOS and FinFFET. This investigation is using Predictive Technology Model (PTM) with various process size (180nm~16nm) bulk MOSFET and FinFET45-nm with different mode. The results proof that when technology scales down, leakage energy becomes higher and author investigate that FinFET 45nm is not capable to minimize leakage power.

Keywords: Power consumption, Leakage power reduction, adiabatic circuit, Single-Rail, Dual-Rail, CMOS, FinFET.