FECT

Abstract: Differential power analysis (DPA) is the most powerful attacks to be considered in designing logic circuit for crypto devices. To maintain the confidentiality and the authentication of secure information processed in crypto devices, several logic techniques to balance current traces of different input-output transitions were reported, such as adopting conventional dual-rail CMOS technique and dual-rail adiabatic logic technique. In this paper, we investigate and compare the previously published dual-rail secure adiabatic logic into 4-bit AES S-box circuit using 0.18 μm CMOS technology with 1.8 V nominal voltage. We evaluate the circuit’s resistivity by observing power fluctuation of 4-bit S-box logic circuits using statistical calculation, such as normalized energy deviation (NED) and normalized standard deviation (NSD). In addition, the minimum energy point is identified for each circuit topology within the frequency range of 10 KHz – 125 MHz.

Keywords: DPA, S-box, dual-rail logic, adiabatic logic, low-power.